1. Field of the Invention
The present invention relates to an input/output controller apparatus and particularly, to an input/output controller apparatus connected between channels of a host system and peripherals, for tracing channel interface signals.
2. Description of the Related Art
Such an input/output controller apparatus is known which is connected between channels of a host system and peripherals including a printer and a CRT display for controlling a sequence of input and output actions between the same.
For evaluating of, or for examining an unwanted event in, a system including the known input/output controller apparatus, the apparatus traces channel interface signals transmitted from the host system via the channels to the apparatus and from the apparatus via the channels to the host system.
FIG. 20 is a schematic system diagram showing an arrangement of the known input/output controller apparatus for tracing the channel interface signals. As shown, the known input/output controller apparatus comprises a ROM 52 for storing control programs or the like, a RAM 54 used as a work area for performing the control programs, a trace controller 55 for collecting and saving trace information in the tracing, a channel controller 60 for controlling a sequence of input and output actions of the channel interface signals, and a CPU 50 for controlling the overall operation of the input/output controller apparatus which all are connected to one another by a CPU bus 80.
The channel controller 60 is connected by a host channel cable 38 to the channels of the host system (not shown) for transmitting to and receiving from the channel of the host system channel controller 60 the channel interface signals. The host channel cable 38 branches to be connected to the trace controller 55. This allows the trace controller 55 to intercept the channel interface signals which are transmitted between the channels of the host system and the channel controller 60.
FIGS. 21 and 22 are block diagrams showing examples of conventional trace logic circuits for implementing the trace controller 55. The trace logic circuit shown in FIG. 21 is designed for sampling the channel interface signal at intervals of a given time. The trace logic circuit shown in FIG. 22 samples the channel interface signal at its points of change.
The trace logic circuit shown in FIG. 21 comprises a counter 100 for producing a storage address for the channel interface signal 76 in synchronization with a clock signal 122, a RAM 102 for storing the channel interface signal 76, a selector 114 responsive to a switching signal 132 for selectively connecting the RAM 102 to either a register 104 or the CPU bus 80, and the register 104 for synchronizing the channel interface signal 76 with a clock signal 122 to output the signal 76.
The counter 100 is connected between the CPU bus 80 and the RAM 102 which in turn is connected to the selector 114. The selector 114 is connected to the CPU bus 80 and the register 104. The input of the register 104 is further connected to a channel of the host system (not shown) for receiving the channel interface signal 76.
The tracing action in the known input/output controller apparatus shown in FIGS. 20 and 21 will now be explained in brief. It is assumed that the counter 100 and the RAM 102 are cleared at the beginning.
Upon receiving a command of starting the communication from an upper device (not shown), the CPU 50 retrieves a corresponding control program from the ROM 52 and actuates the channel controller 60 to start the communication with the channel of the host system as well as actuates the trace logic circuit in the trace controller 55. When having supplied the selector 114 with a switching signal 132 for directing the selector 114 to connect the RAM 102 to the register 104, the CPU 50 allows the counter 100 and the register 104 to receive a predetermined clock signal 122 format.
The counter 100 counts up in synchronization with the clock signal 122 from the CPU 50, delivering its count as an address signal to an address bus 120 in a sequential manner. The address signal on the address bus 120 is transferred to the RAM 102 for defining a storage location of received data.
The register 104 is also responsive to the same clock signal 122 which is supplied from the CPU 50 to the counter 100 and, is synchronized with the clock signal 122, in other words, is synchronized with the counting up of the counter 100 to transmit the channel interface signal 76.
The above procedure allows the channel interface signal 76 from the register 104 to be sequentially stored in the RAM 102 in response to the address signal from the counter 100.
As for specific length (period of time) the channel interface signals 76 have been stored, the CPU 50 supplies a predetermined switching signal 132 to the selector 114 for connecting the RAM 102 to the CPU bus 80 and then, retrieves the channel interface signal 76 from the RAM 102 via the selector 114 and the CPU bus 80 before transmitting it to the upper device (not shown). The channel interface signal 76 is received and edited by the upper device for outputting data on the display or the printer (not shown).
FIG. 23 is a timing chart showing fourteen kinds of the channel interface signals (ADR Out, SEL Out, . . . , DAT In) for communications with the known input/output controller apparatus illustrated in FIGS. 20 and 21. The timing chart includes a series of sampling points, shown at bottom, for the channel interface signal 76 in the trace controller 55. As apparent, the sampling timing in the trace controller 55 are aligned at equal intervals of a time synchronized with the clock signal 122.
The trace logic circuit shown in FIG. 22 is explained.
As shown in FIG. 22, the trace logic circuit comprises a counter 100, a RAM 102, a selector 114, a couple of registers 104 and 106, a comparator 108, and an AND gate 112.
The register 104 is provided for synchronizing the channel interface signal 76 while the register 106 is for delaying the channel interface signal by one clock unit before comparison.
The comparator 108 compares data from the resistor 104 and data from the resistor 106. Its output signal 128 is low when the two data are identical and high when not.
The AND gate 112 is provided for receiving the output signal 128 of the comparator 108 and the clock signal 122. It is turned on when the output signal 128 of the comparator 108 only is high, transmitting the clock signal 122 to one clock input of the counter 100. More specifically, only when the two data from the resistors 104 and 106 are not identical to each other, the counter 100 is synchronized with and activated by the clock signal 122 for counting up.
The other components than the comparator 108, the resistor 106, and the AND gate 112 are identical to those of the prescribed trace logic circuit shown in FIG. 21 and will be explained in no more detail.
The tracing in the input/output controller apparatus shown in FIGS. 20 and 22 is explained in brief. It is also assumed that the counter 100 and the RAM 102 are cleared at the beginning.
Upon receiving a command for starting the communication from an upper device (not shown), the CPU 50 retrieves a corresponding control program from the ROM 52 and actuates the channel controller 60 to connect with the channels of the host system as well as the trace logic circuit in the trace controller 55. The CPU 50 supplies the selector 114 with the switching signal 132 for connecting the RAM 102 to the resistor 106 and then, delivers the clock signal 122 to the other input of the AND gate 112 and the clock inputs of both the resisters 104 and 106.
The register 104 transmits the channel interface signal 76 in synchronization with the clock signal 122 and the resister 106 transmits the channel interface signal 76 input from the register 104 in synchronization with the clock signal 122. More particularly, the register 106 constantly releases a form of the channel interface signal which precedes the channel interface signal received from the register 104 by one clock unit.
The comparator 108 compares the channel interface signal output of the register 104 and the channel interface signal output of the register 106 and delivers its result of comparison as the output signal 128 to the AND gate 112.
When the two channel interface signal outputs of both the registers 104 and 106 are identical to each other, the output signal 128 of the comparator 108 is low thus disabling the AND gate 112 and not allowing the counting up in the counter 100. If the two outputs are different, that is, the channel interface signal has a change, the output signal 128 of the comparator 108 is turned to high, hence turning on the AND gate 112 and allowing the counter 100 to count up.
In this manner, the address signal to be supplied to the RAM 102 is counted up by the counter 100 and used for storing data in the corresponding location in the RAM 102. More specifically, each updating of the address signal with the counter 100 permits the channel interface signal output 76 of the register 106 to be saved in the RAM 102.
Upon having a change, the channel interface signal 76 from the register 106 is stored in the address of the RAM 102 which is defined by the address signal of the counter 100 at every changing the channel interface signal.
When a predetermined length of the channel interface signal 76 has been stored, the CPU 50 supplies the selector 114 with another mode of the switching signal 132 for connecting the RAM 102 to the CPU bus 80 and then, retrieves the channel interface signal 76 stored in the RAM 102 via the selector 114 and the CPU bus 80 before sending it to the upper device not shown. The channel interface signal 76 is received and edited by the upper device for outputting on the display or the printer not shown.
FIG. 24 is a timing chart showing fourteen kinds of the channel interface signals (ADR Out, SEL Out, . . . , DAT In) for communications with the known input/output controller apparatus illustrated in FIGS. 20 and 22. The timing chart includes a series of sampling points, shown at bottom, for the channel interface signal 76 in the trace controller 55. As apparent, the sampling timing in the trace controller 55 are timed with the changes in the channel interface signal 76.
In a technique disclosed in Japanese Patent Application Laid-open (JP-A) No. 6-89240, a tracing action is made with at least one of the two trace logic circuits shown in FIGS. 21 and 22 installed in a peripheral device.
The technique disclosed in Japanese Patent Application Laid-open (JP-A) No. 6-89240 may however fail to detect a change in the channel interface signal which is shorter in time than the sampling period if the sampling period is long. If the sampling period is too short, the total of data stored in the memory will be increased thus requiring a large size of the storing capacity.
Should the two trace logic circuits shown in FIGS. 21 and 22 be provided together for switching from one to the other depending on the tracing action, they need a considerable size of the installation area in a package.
Since the analyzation of such a state as an unwanted event is carried out with the use of the information of sampled in the above manner, i.e., only the channel interface signal, it will hardly be decreased in the consumption of time and increased in the accuracy.
In addition, the foregoing trace logic circuits are assigned to specific host systems respectively and when another host system of which a command and a sequence of input and output actions may be different is used, they have to be replaced with a corresponding trace logic circuit.